1. Field of the Invention
The present invention is directed to DC-DC switched mode power converters. More particularly, the present invention is directed to a method and apparatus for providing virtual current sensing capabilities in DC-DC switched mode power converters.
2. The Background
Switched mode DC-DC power converters are common in the electronics industry. They are frequently used to convert one available DC level voltage to another DC level voltage, often needed for a particular set of semiconductor chips. Such power converters generally use one or more electrically controlled switches (such as N- or P-Channel MOSFETs), the gates of which are controlled by a switched mode power supply controller circuit which is often integrated onto a single chip.
A typical synchronous DC-DC pulse-width modulated (xe2x80x9cPWMxe2x80x9d) converter 100 in a step-down buck converter configuration is shown in FIG. 1. A drive signal D generated within control circuitry 110 is routed to drive logic 115, which generates the HI and LO signals. The controller drive logic 115 modulates the HI and LO signals to alternatively turn ON and turn OFF the output transistor switches, MUPPER and MLOWER in switch block 120. This alternate turning ON and OFF of the switches creates a square wave on the SW node, whose duty cycle is equal to (VOUT/VIN). Switches MUPPER and MLOWER control the voltage at the phase node, SW. When MUPPER is on, the phase node, SW, is at VIN (a first input voltage). When MLOWER is on, the phase node, SW, is at ground, 130 (a second input voltage).
In the context of the present invention, duty cycle is defined as the ON-time (or pulse width) of a pulse divided by the period of that waveform. As those of ordinary skill in the art will recognize, the square wave on the SW node is averaged by the output filter made up of inductor LOUT and capacitor COUT to produce an output voltage determined by the expression VOUT=VFB*(1+(R1/R2)). Ideally, the converter is intended to provide output current up to some preset limit with no change in output voltage. As is well known to those of ordinary skill in the art, the current sense resistor, RSENSE, is traditionally used to obtain a voltage VRsense=(IL*RSENSE), where IL is the current through the inductor LOUT. The voltage across the current sense resistor RSENSE is reported to the control circuitry 110 via the CSH (xe2x80x9ccurrent sense highxe2x80x9d) and CSL (xe2x80x9ccurrent sense lowxe2x80x9d) signals. Also, the output voltage VOUT is reported to control circuitry 110 via the CSL signal and the FB signal, which is derived from the voltage divider network formed by resistors R1 and R2. Additional details necessary for practically implementing typical control circuitry 110 are well known to those of ordinary skill in the art, and are not discussed in further detail herein so as not to overcomplicate the present disclosure.
Still referring to FIG. 1, the shape of the voltage waveform across RSENSE is triangular, where the rising slope can be expressed as follows:
rising slope=RSENSE*(VINxe2x88x92VOUT)/LOUT
The falling slope of this triangular voltage slope can be expressed as follows:
falling slope=xe2x88x92RSENSE*(VOUT/LOUT).
This triangular current signal is summed with an internal ramp signal (for duty cycles  greater than 50%) and compared with an output voltage error signal to determine the HI and LO signal modulation. As those of ordinary skill in the art will recognize, this closed loop control scheme for output voltage regulation is known as peak current-mode control.
FIG. 2 is a timing diagram illustrating some of switching waveforms for the circuit of FIG. 1. The D (xe2x80x9cdrivexe2x80x9d) waveform alternates between an ON time (e.g., the time between time points 210-A and 212-A in FIG. 2) and an OFF time (e.g., the time between time points 210-A and 212-A in FIG. 2). The time between the rising edge of the ON time (e.g., at time point 210-A shown in FIG. 2) and time rising edge of the next ON time (e.g., at time point 210-B shown in FIG. 2) is defined as a xe2x80x9cphasexe2x80x9d (or xe2x80x9cswitching cyclexe2x80x9d) in the context of the present invention. In a fixed frequency converter, the phase time is determined by an oscillator or other clock source, and the duty cycle is varied to regulate the output voltage, VOUT. On the other hand, in a variable frequency converter, the phase time is varied and the ON time typically remains constant to regulate the output voltage, VOUT.
Still referring to FIG. 2, the voltage across the phase node, SW, essentially follows the waveform of the drive signal D, and alternates in value between VIN (during the ON time) and ground (during the OFF time). The HI waveform (which controls the MUPPER transistor switch) is essentially 180 degrees out of phase with the LO waveform (which controls the MLOWER transistor switch). As shown in FIG. 2 (with exaggeration, for the sake of explanation) the HI waveform is typically turned OFF slightly before the LO waveform is turned ON to prevent a short circuit or cross conduction condition. Similarly, the LO waveform is typically turned OFF slightly before the HI waveform is turned ON. VL is the voltage across the primary winding of inductor LOUT. VL switches between (VINxe2x88x92VOUT) (when the HI waveform is ON) and (xe2x88x92VOUT) (when the HI waveform is OFF), essentially following the HI signal. VOUT is filtered by output capacitor COUT producing a DC output equal to D*Vin with a small ripple voltage that follows the polarity of the VL voltage. None of the waveforms are drawn to scale in FIG. 2, and their values/excursions have been exaggerated in some cases for the sake of clearer explanation.
Various alternative implementations for the switch block 120 of FIG. 1 are known to those of ordinary skill in the art, some of which are illustrated in FIG. 3. Referring to FIG. 3, the MLOWER transistor switch may also be implemented as a diode D1 as shown in diagram 120-A, or as a transistor connected as a diode in diagrams 120-B and 120-C. Moreover, many other DC-DC converter configurations using current-mode control are known to those of ordinary skill in the art (e.g., boost converters, Cuk converters, step-up configurations, multiple output configurations, fixed frequency converters, variable frequency converters, etc.). As will be described in more detail later in this document, all of these various configurations may implement the virtual current sensing technique according to aspects of the present invention.
Several disadvantages are associated with the method of inductor current sensing described above with reference to FIGS. 1 and 2. First, the DC value of the voltage across the current sensing resistor RSENSE introduces an output voltage regulation error proportional to DC output current. Second, the signal-to-noise ratio (xe2x80x9cSNRxe2x80x9d) of the AC portion (or slope amplitude) of the voltage across the current sensing resistor RSENSE is low due to switching noise induced from parasitic noise elements in the system. This noise causes inaccuracies in the measured inductor current slope that could result in converter instability and possibly failure. Also, power (having value P=[IL2*RSENSE]) is dissipated through the RSENSE resistor, and this reduces the overall converter efficiency.
Another method known to those of ordinary skill in the art for sensing inductor current is to measure the voltage drop across the MUPPER or MLOWER MOSFET (metal oxide semiconductor field-effect transistor) switches when either one is turned ON. This voltage, VDS, is equal to the inductor current during the transistor""s on-time, IDS, multiplied by the on-resistance, RDS(ON), of the transistor. Since different types of MOSFETs have different RDS(ON) values, a reference must be programmed into the controller to interpret the relationship between VDS and IDS. This technique exhibits the following disadvantages in terms of inductor current sensing. First, as is known to those of ordinary skill in the art, the RDS(ON) of a MOSFET changes considerably over temperature, and this causes the measurement accuracy of IL to be highly temperature-dependent. Also, the SNR of the measured VDS is relatively low, due to short measurement time constraints (measuring over a fraction of the total switching period) and switching noise induced from parasitic noise elements in the system. This noise causes inaccuracies in the measured inductor current, which may result in converter instability and possibly failure of the converter.
Thus, a need exists for an improved current sensing technique. The virtual current sensing technique according to aspects of the present invention is intended to eliminate the disadvantages associated with using a current sense resistor or RDS(ON) sensing. These and other features and advantages of the present invention will be presented in more detail in the following specification of the invention and in the associated figures.
The external current sensing resistor which is typically an essential component of current-mode controlled switched mode power converters is eliminated, and replaced with a virtual current sensing apparatus and method, which may be integrated with PWM controller circuitry. In a fixed frequency implementation, when a switching phase begins, the high-side switching transistor is turned on, causing a phase node to go high. At this point, a current sensing capacitor begins to be charged by a first programmable current source or transconductance amplifier, and the voltage across the current sensing capacitor simulates the rising slope of the traditional triangular current sensing resistor voltage. At the same time, a ramp capacitor is reset to a reference voltage and begins to be charged by a second programmable current source or transconductance amplifier. As part of the normal operation of the power converter, an error amplifier compares a feedback voltage signal, which may be based on a voltage divider and the output voltage of the power converter, with the reference voltage. When a current ramp which is a function of the sum of the voltages across the current sensing capacitor and the ramp capacitor exceeds a current corresponding to the error voltage output of the error amplifier, the drive signal to the high-side switching transistor is turned off, causing the phase node to go low. At this point, the current sensing capacitor begins to be discharged by a third programmable current source or transconductance amplifier, and the voltage across the current sensing capacitor simulates the falling slope of the traditional triangular current sensing resistor voltage. When the switching phase time expires, the high-side switching transistor is again turned on, and the cycle repeats.